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Low Capacitance, 16- and 8-Channel 15 V/+12 V iCMOSTM Multiplexers ADG1206/ADG1207
FEATURES
<1 pC charge injection over full signal range 1.5 pF off capacitance 33 V supply range 120 on resistance Fully specified at 15 V/+12 V 3 V logic-compatible inputs Rail-to-rail operation Break-before-make switching action 28-lead TSSOP and 32-lead, 5 mm x 5 mm LFCSP_VQ
S1
FUNCTIONAL BLOCK DIAGRAMS
ADG1206
S1A DA S8A D S1B DB S16 1-OF-16 DECODER S8B 1-OF-8 DECODER
06119-001
ADG1207
APPLICATIONS
Audio and video routing Automatic test equipment Data acquisition systems Battery-powered systems Sample-and-hold systems Communication systems
A0 A1 A2 A3 EN
A0 A1 A2 EN
Figure 1.
GENERAL DESCRIPTION
The ADG1206 and ADG1207 are monolithic iCMOS analog multiplexers comprising sixteen single channels and eight differential channels, respectively. The ADG1206 switches one of sixteen inputs to a common output, as determined by the 4bit binary address lines A0, A1, A2, and A3. The ADG1207 switches one of eight differential inputs to a common differential output, as determined by the 3-bit binary address lines A0, A1, and A2. An EN input on both devices is used to enable or disable the device. When disabled, all channels are switched off. When on, each channel conducts equally well in both directions and has an input signal range that extends to the supplies. The iCMOS (industrial CMOS) modular manufacturing process combines high voltage CMOS (complementary metaloxide semiconductor) and bipolar technologies. It enables the development of a wide range of high performance analog ICs capable of 33 V operation in a footprint that no other generation of high voltage parts has been able to achieve. Unlike analog ICs using conventional CMOS processes, iCMOS components can tolerate high supply voltages while providing increased performance, dramatically lower power consumption, and reduced package size.
The ultralow capacitance and exceptionally low charge injection of these multiplexers make them ideal solutions for data acquisition and sample-and-hold applications, where low glitch and fast settling are required. Figure 2 shows that there is minimum charge injection over the entire signal range of the device. iCMOS construction also ensures ultralow power dissipation, making the parts ideally suited for portable and battery-powered instruments.
1.0 MUX (SOURCE TO DRAIN) 0.9 TA = 25C 0.8
CHARGE INJECTION (pC)
0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -15 -10 VDD = +5V VSS = -5V -5 0 VS (V) 5 10 15
06119-002
VDD = +15V VSS = -15V
VDD = +12V VSS = 0V
Figure 2. Source-to-Drain Charge Injection vs. Source Voltage
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved.
ADG1206/ADG1207 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagrams............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Dual Supply ................................................................................... 3 Single Supply ................................................................................. 5 Absolute Maximum Ratings ............................................................7 ESD Caution...................................................................................7 Pin Configurations and Function Descriptions ............................8 Typical Performance Characteristics ........................................... 12 Terminology .................................................................................... 16 Test Circuits..................................................................................... 17 Outline Dimensions ....................................................................... 19 Ordering Guide .......................................................................... 19
REVISION HISTORY
7/06--Revision 0: Initial Version
Rev. 0 | Page 2 of 20
ADG1206/ADG1207 SPECIFICATIONS
DUAL SUPPLY
VDD = +15 V 10%, VSS = -15 V 10%, GND = 0 V, unless otherwise noted. 1 Table 1.
Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On Resistance Match Between Channels, RON On Resistance Flatness, RFLAT (On) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 2 Transition Time, tTRANSITION tON (EN) tOFF (EN) Break-Before-Make Time Delay, tBBM Charge Injection Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion + Noise -3 dB Bandwidth ADG1206 -3 dB Bandwidth ADG1207 CS (Off ) CD (Off ) ADG1206 CD (Off ) ADG1207 +25C -40C to +85C -40C to +125C VSS to VDD 120 200 3.5 6 20 64 0.03 0.2 0.05 0.2 0.08 0.2 0.6 0.6 0.6 1 2 2 2.0 0.8 0.005 0.1 2 80 130 75 95 85 100 20 0.5 -85 -85 0.15 280 490 1.5 2 11 12 7 9 240 270 Unit V typ max typ max typ max nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max pF typ ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ % typ MHz typ MHz typ pF typ pF max pF typ pF max pF typ pF max Test Conditions/Comments
VS = 10 V, IS = -1 mA; see Figure 28 VDD = +13.5 V, VSS = -13.5 V VS = 10 V, IS = -1 mA
10 76
12 83
VS = -5 V, 0 V, +5 V; IS = -1 mA
VD = 10 V, VS = 10 V; see Figure 29 VS = 1 V, 10 V; VD = 10 V, 1 V; see Figure 29 VS = VD = 10 V; see Figure 30
VIN = VINL or VINH
165 105 125
185 115 140 10
RL = 300 , CL = 35 pF VS = 10 V; see Figure 31 RL = 300 , CL = 35 pF VS = 10 V; see Figure 33 RL = 300 , CL = 35 pF VS = 10 V; see Figure 33 RL = 300 , CL = 35 pF VS1 = VS2 = 10 V; see Figure 32 VS = 0 V, RS = 0 , CL = 1 nF; see Figure 34 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 35 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 37 RL = 10 k, 5 V rms, f = 20 Hz to 20 kHz; see Figure 38 RL = 50 , CL = 5 pF; see Figure 36 RL = 50 , CL = 5 pF; see Figure 36 f = 1 MHz, VS = 0 V f = 1 MHz, VS = 0 V f = 1 MHz, VS = 0 V f = 1 MHz, VS = 0 V f = 1 MHz, VS = 0 V f = 1 MHz, VS = 0 V
Rev. 0 | Page 3 of 20
ADG1206/ADG1207
Parameter CD, CS (On) ADG1206 CD, CS (On) ADG1207 POWER REQUIREMENTS IDD IDD ISS VDD/VSS
1 2
+25C 13 15 8 10 0.002
-40C to +85C
-40C to +125C
Unit pF typ pF max pF typ pF max A typ A max A typ A max A typ A max V min/max
Test Conditions/Comments f = 1 MHz, VS = 0 V f = 1 MHz, VS = 0 V f = 1 MHz, VS = 0 V f = 1 MHz, VS = 0 V VDD = +16.5 V, VSS = -16.5 V Digital inputs = 0 V or VDD Digital inputs = 5 V Digital inputs = 0 V, 5 V, or VDD GND = 0V
1.0 260 420 0.002 1.0 5/16.5
Temperature range for Y version is -40C to +125C. Guaranteed by design, not subject to production test.
Rev. 0 | Page 4 of 20
ADG1206/ADG1207
SINGLE SUPPLY
VDD = 12 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. 1 Table 2.
Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On Resistance Match Between Channels, RON On Resistance Flatness, RFLAT (On) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 2 Transition Time, tTRANSITION tON (EN) tOFF (EN) Break-Before-Make Time Delay, tBBM Charge Injection Off Isolation Channel-to-Channel Crosstalk -3 dB Bandwidth ADG1206 -3 dB Bandwidth ADG1207 CS (Off ) CD (Off ) ADG1206 CD (Off ) ADG1207 CD, CS (On) ADG1206 CD, CS (On) ADG1207 +25C -40C to +85C -40C to +125C 0 to VDD 300 475 5 16 60 0.02 0.2 0.05 0.2 0.08 0.2 567 625 Unit V typ max typ max typ nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max pF typ ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ MHz typ MHz typ pF typ pF max pF typ pF max pF typ pF max pF typ pF max pF typ pF max Test Conditions/Comments
VS = 0 V to10 V, IS = -1 mA; see Figure 28 VDD = 10.8 V, VSS = 0 V VS = 0 V to 10 V, IS = -1 mA
26
27
VS = 3 V, 6 V, 9 V; IS = -1 mA VDD = 13.2 V VS = 1 V/10 V, VD = 10 V/1 V; see Figure 29 VS = 1 V/10 V, VD = 10 V/1 V; see Figure 29 VS = VD = 1 V or 10 V; see Figure 30
0.6 0.6 0.6
1 2 2 2.0 0.8
0.001 0.1 3 100 140 80 100 90 110 25 0.2 -85 -85 185 300 1.5 2 13 15 9 11 15 17 10 12
VIN = VINL or VINH
175 120 130
200 130 155 15
RL = 300 , CL = 35 pF VS = 8 V; see Figure 31 RL = 300 , CL = 35 pF VS = 8 V; see Figure 33 RL = 300 , CL = 35 pF VS = 8 V; see Figure 33 RL = 300 , CL = 35 pF VS1 = VS2 = 8 V; see Figure 32 VS = 6 V, RS = 0 , CL = 1 nF; see Figure 34 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 35 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 37 RL = 50 , CL = 5 pF; see Figure 36 RL = 50 , CL = 5 pF; see Figure 36 f = 1 MHz, VS = 6 V f = 1 MHz, VS = 6 V f = 1 MHz, VS = 6 V f = 1 MHz, VS = 6 V f = 1 MHz, VS = 6 V f = 1 MHz, VS = 6 V f = 1 MHz, VS = 6 V f = 1 MHz, VS = 6 V f = 1 MHz, VS = 6 V f = 1 MHz, VS = 6 V
Rev. 0 | Page 5 of 20
ADG1206/ADG1207
Parameter POWER REQUIREMENTS IDD IDD VDD
1 2
+25C 0.002
-40C to +85C
-40C to +125C
Unit A typ A max A typ A max V min/max
Test Conditions/Comments VDD = 13.2 V Digital inputs = 0 V or VDD Digital inputs = 5 VSS = 0 V, GND = 0 V
1.0 260 420 5/16.5
Temperature range for Y version is -40C to +125C. Guaranteed by design, not subject to production test.
Rev. 0 | Page 6 of 20
ADG1206/ADG1207 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 3.
Parameter VDD to VSS VDD to GND VSS to GND Analog, Digital Inputs 1 Rating 35 V -0.3 V to +25 V +0.3 V to -25 V VSS - 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first 30 mA 100 mA
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time.
Continuous Current, S or D Peak Current, S or D (Pulsed at 1 ms, 10% Duty Cycle Maximum) Operating Temperature Ranges Industrial (Y Version) Storage Junction Temperature 28-Lead TSSOP JA, Thermal Impedance JC, Thermal Impedance 32-Lead LFCSP_VQ JA, Thermal Impedance Reflow Soldering Peak Temperature (Pb-Free)
1
-40C to +125C -65C to +150C 150C 97.9C/W 14C/W 27.27C/W 260(+0/-5)C
Overvoltages at A, EN, S, or D are clamped by internal diodes. Current should be limited to the maximum ratings given.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 7 of 20
ADG1206/ADG1207 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VDD NC NC S16 S15 S14 S13 S12 S11
1 2 3 4 5 6 7 8 9 28 27 26 25 24
D VSS S8 S7 S6 S5 S4 S3 S2 S1 EN A0 A1
ADG1206
TOP VIEW (Not to Scale)
23 22 21 20 19 18 17 16 15
S10 10 S9 11 GND 12 NC 13 A3 14
S16 S15 S14 S13 S12 S11 S10 S9
1 2 3 4 5 6 7 8
32 31 30 29 28 27 26 25
NC VDD NC D NC NC NC VSS
PIN 1 INDICATOR
ADG1206
TOP VIEW (Not to Scale)
24 23 22 21 20 19 18 17
S8 S7 S6 S5 S4 S3 S2 S1
06119-004
A2
06119-003
NC = NO CONNECT
NC = NO CONNECT
Figure 3. ADG1206 Pin Configuration--TSSOP
Figure 4. ADG1206 Pin Configuration--5 mm x 5 mm LFCSP_VQ, Exposed Pad Tied to Substrate, VSS
Table 4. ADG1206 Pin Function Descriptions
TSSOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Pin Number LFCSP_VQ 31 12, 13 26, 27, 28, 30, 32 1 2 3 4 5 6 7 8 9 - 10 11 14 15 16 17 18 19 20 21 22 23 24 25 29 Mnemonic VDD NC NC S16 S15 S14 S13 S12 S11 S10 S9 GND NC A3 A2 A1 A0 EN S1 S2 S3 S4 S5 S6 S7 S8 VSS D Description Most Positive Power Supply Potential. No Connect. No Connect. Source Terminal 16. Can be an input or an output. Source Terminal 15. Can be an input or an output. Source Terminal 14. Can be an input or an output. Source Terminal 13. Can be an input or an output. Source Terminal 12. Can be an input or an output. Source Terminal 11. Can be an input or an output. Source Terminal 10. Can be an input or an output. Source Terminal 9. Can be an input or an output. Ground (0 V) Reference. No Connect. Logic Control Input. Logic Control Input. Logic Control Input. Logic Control Input. Active High Digital Input. When this pin is low, the device is disabled and all switches are turned off. When this pin is high, the Ax logic inputs determine which switch is turned on. Source Terminal 1. Can be an input or an output. Source Terminal 2. Can be an input or an output. Source Terminal 3. Can be an input or an output. Source Terminal 4. Can be an input or an output. Source Terminal 5. Can be an input or an output. Source Terminal 6. Can be an input or an output. Source Terminal 7. Can be an input or an output. Source Terminal 8. Can be an input or an output. Most Negative Power Supply Potential. In single-supply applications, this pin can be connected to ground. Drain Terminal. Can be an input or an output.
Rev. 0 | Page 8 of 20
GND A3 A2 NC NC A1 A0 EN
9 10 11 12 13 14 15 16
ADG1206/ADG1207
Table 5. ADG1206 Truth Table
A3 X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A2 X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 EN 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 On Switch None 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Rev. 0 | Page 9 of 20
ADG1206/ADG1207
VDD DB NC S8B S7B S6B S5B S4B S3B
1 2 3 4 5 6 7 8 9 28 27 26 25 24
DA VSS S8A S7A S6A S5A S4A S3A S2A S1A EN A0 A1 A2
06119-036
ADG1207
TOP VIEW (Not to Scale)
22 21 20 19 18 17 16 15
S2B 10 S1B 11 GND 12 NC 13 NC 14
S8B S7B S6B S5B S4B S3B S2B S1B
1 2 3 4 5 6 7 8
32 31 30 29 28 27 26 25
23
NC DB NC VDD NC DA NC VSS
PIN 1 INDICATOR
ADG1207
TOP VIEW (Not to Scale)
24 23 22 21 20 19 18 17
S8A S7A S6A S5A S4A S3A S2A S1A
06119-037
NC = NO CONNECT
NC = NO CONNECT
Figure 5. ADG1207 Pin Configuration--TSSOP
Figure 6. ADG1207 Pin Configuration--5 mm x 5 mm LFCSP_VQ Exposed Pad Tied to Substrate, VSS
Table 6. ADG1207 Pin Function Descriptions
TSSOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Pin Number LFCSP_VQ 29 31 11, 12, 13 1 2 3 4 5 6 7 8 9 26, 28, 30, 32 - 10 14 15 16 17 18 19 20 21 22 23 24 25 27 Mnemonic VDD DB NC S8B S7B S6B S5B S4B S3B S2B S1B GND NC NC A2 A1 A0 EN S1A S2A S3A S4A S5A S6A S7A S8A VSS DA Description Most Positive Power Supply Potential. Drain Terminal B. Can be an input or an output. No Connect. Source Terminal 8B. Can be an input or an output. Source Terminal 7B. Can be an input or an output. Source Terminal 6B. Can be an input or an output. Source Terminal 5B. Can be an input or an output. Source Terminal 4B. Can be an input or an output. Source Terminal 3B. Can be an input or an output. Source Terminal 2B. Can be an input or an output. Source Terminal 1B. Can be an input or an output. Ground (0 V) Reference. No Connect. No Connect. Logic Control Input. Logic Control Input. Logic Control Input. Active High Digital Input. When this pin is low, the device is disabled and all switches are turned off. When this pin is high, the Ax logic inputs determine which switch is turned on. Source Terminal 1A. Can be an input or an output. Source Terminal 2A. Can be an input or an output. Source Terminal 3A. Can be an input or an output. Source Terminal 4A. Can be an input or an output. Source Terminal 5A. Can be an input or an output. Source Terminal 6A. Can be an input or an output. Source Terminal 7A. Can be an input or an output. Source Terminal 8A. Can be an input or an output. Most Negative Power Supply Potential. In single-supply applications, this pin can be connected to ground. Drain Terminal A. Can be an input or an output.
Rev. 0 | Page 10 of 20
GND A2 NC NC NC A1 A0 EN
9 10 11 12 13 14 15 16
ADG1206/ADG1207
Table 7. ADG1207 Truth Table
A2 X 0 0 0 0 1 1 1 1 A1 X 0 0 1 1 0 0 1 1 A0 X 0 1 0 1 0 1 0 1 EN 0 1 1 1 1 1 1 1 1 On Switch Pair None 1 2 3 4 5 6 7 8
Rev. 0 | Page 11 of 20
ADG1206/ADG1207 TYPICAL PERFORMANCE CHARACTERISTICS
200 180 160
ON RESISTANCE ()
250 TA = 25C VDD = +13.5V VSS = -13.5V
ON RESISTANCE ()
VDD = +15V VSS = -15V 200 TA = +125C 150 TA = +85C TA = +25C 100 TA = -40C 50
VDD = +15V VSS = -15V
140 120 100 80 60 40 20 -9 -6 -3 0 3 6 9 SOURCE OR DRAIN VOLTAGE (V) 12 15 18
06119-005
VDD = +16.5V VSS = -16.5V
-10
-5 0 5 SOURCE OR DRAIN VOLTAGE (V)
10
15
Figure 7. On Resistance as a Function of VD (VS) for Dual Supply
Figure 10. On Resistance as a Function of VD (VS) for Different Temperatures, Dual Supply
600
600 TA = 25C 500
ON RESISTANCE ()
VDD = +4.5V VSS = -4.5V
500
ON RESISTANCE ()
TA = +125C
VDD = 12V VSS = 0V
VDD = +5V VSS = -5V 400
TA = +85C 400 TA = +25C 300 TA = -40C
300
VDD = +5.5V VSS = -5.5V
200
200
100
100
06119-006
-6
-4
-2 0 2 SOURCE OR DRAIN VOLTAGE (V)
4
6
0
2
4 6 8 SOURCE OR DRAIN VOLTAGE (V)
10
12
Figure 8. On Resistance as a Function of VD (VS) for Dual Supply
Figure 11. On Resistance as a Function of VD (VS) for Different Temperatures, Single Supply
1200
450 400 350
ON RESISTANCE ()
TA = 25C
VDD = 10.8V VSS = 0V VDD = 12V VSS = 0V
LEAKAGE (pA)
1000 800 600 400 200 0 -200 -400 -600 -800
VDD = +15V VSS = -15V VBIAS = +10V/-10V
ID (OFF) - + ID, IS (ON) + + IS (OFF) + -
300 250 200 150 100 50
VDD = 13.2V VSS = 0V
IS (OFF) - + ID (OFF) + -
-1000
06119-007
0
2
4 6 8 10 SOURCE OR DRAIN VOLTAGE (V)
12
14
0
20
40
60 80 TEMPERATURE (C)
100
120
Figure 9. On Resistance as a Function of VD (VS) for Single Supply
Figure 12. ADG1206 Leakage Currents as a Function of Temperature, Dual Supply
Rev. 0 | Page 12 of 20
06119-010
0
-1200
ID, IS (ON) - -
06119-009
0
0
06119-008
0 -18 -15 -12
0 -15
ADG1206/ADG1207
400 300 200
LEAKAGE (pA)
6
VDD = 12V VSS = 0V VBIAS = 1V/10V
ID (OFF) - +
4
DEMUX (DRAIN TO SOURCE) TA = 25C VDD = +5V VSS = -5V
ID, IS (ON )+ +
CHARGE INJECTION (pC)
IS (OFF) + -
2
100 0 -100 -200 -300
06119-011
0 VDD = +15V VSS = -15V
VDD = +12V VSS = 0V
-2
IS (OFF) - + ID (OFF) + -
-4
0
20
40
60 80 TEMPERATURE (C)
100
120
-10
-5
0 VS (V)
5
10
15
Figure 13. ADG1206 Leakage Currents as a Function of Temperature, Single Supply
Figure 16. Drain-to-Source Charge Injection vs. Source Voltage
200 180 160 140 VDD = +15V VSS = -15V
TIME (ns)
350
IDD PER CHANNEL TA = 25C
300 250 200 150 100 50 0 -40 VDD = +5V VSS = -5V
IDD (A)
120 100 80 60 40 20 0 0 2 4 6 8 10 LOGIC, INX (V) 12 14 16 VDD = +12V VSS = 0V
06119-012
VDD = +12V VSS = 0V VDD = +15V VSS = -15V
-20
0
20
40
60
80
100
120
TEMPERATURE (C)
Figure 14. IDD vs. Logic Level
Figure 17. Transition Time vs. Temperature
1.0
MUX (SOURCE TO DRAIN) 0.9 TA = 25C 0.8
0 -10 -20 VDD = +15V VSS = -15V TA = 25C
CHARGE INJECTION (pC)
OFF ISOLATION (dB)
0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -15 -10 VDD = +5V VSS = -5V -5 0 VS (V) 5 10 15
06119-013
-30 -40 -50 -60 -70 -80 -90 -100 100k 1M 10M FREQUENCY (Hz) 100M 1G
06119-016
VDD = +15V VSS = -15V
VDD = +12V VSS = 0V
-110 10k
Figure 15. Source-to-Drain Charge Injection vs. Source Voltage
Figure 18. Off Isolation vs. Frequency
Rev. 0 | Page 13 of 20
06119-050
06119-014
-400
ID, IS (ON) - -
-6 -15
ADG1206/ADG1207
0 -10 -20 -30 TA = 25C
10 LOAD = 10k TA = 25C
CROSSTALK (dB)
THD + N (%)
-40 -50 -60 -70 -80 -90 -100 100k 1M 10M 100M 1G
06119-051
1
ADJACENT CHANNELS
VDD = +5V, VSS = -5V, VS = +3.5V rms
VDD = +15V, VSS = -15V, VS = +5V rms 0.1
NON ADJACENT CHANNELS
100
FREQUENCY (Hz)
1k FREQUENCY (Hz)
10k
100k
Figure 19. ADG1206 Crosstalk vs. Frequency
Figure 22. THD + N vs. Frequency
0 -10 -20 -30 TA = 25C
20 18 16 VDD = +15V VSS = -15V TA = 25C
CAPACITANCE (pF)
14 12 10 8 6 4
CROSSTALK (dB)
-40 -50 -60 -70 -80 -90 -100 -110 10k 100k 1M 10M NON ADJACENT CHANNELS
06119-052
SOURCE/DRAIN ON
ADJACENT CHANNELS
DRAIN OFF
2
SOURCE OFF -10 -5 0 VBIAS (V) 5 10 15
06119-054 06119-055
100M
1G
0 -15
FREQUENCY (Hz)
Figure 20. ADG1207 Crosstalk vs. Frequency
Figure 23. ADG1206 Capacitance vs. Source Voltage, 15 V Dual Supply
-4 -6 -8 ADG1207
20 18 16 SOURCE/DRAIN ON
ON RESPONSE (dB)
-10 ADG1206 -12 -14 -16
CAPACITANCE (pF)
14 12 10 8 6 4 VDD = 12V VSS = 0V TA = 25C DRAIN OFF
-18
06119-053
-20 10k
VDD = +15V VSS = -15V TA = 25C 100k 1M 10M 100M 1G FREQUENCY (Hz)
2 0 0 2 4
SOURCE OFF
6 VBIAS (V)
8
10
12
Figure 21. On Response vs. Frequency
Figure 24. ADG1206 Capacitance vs. Source Voltage, 12 V Single Supply
Rev. 0 | Page 14 of 20
06119-020
-110 10k
0.01 10
ADG1206/ADG1207
12 VDD = +15V VSS = -15V TA = 25C SOURCE/DRAIN ON
0 -10 -20 -30
AC PSRR (dB)
DRAIN OFF
10
TA = 25C NO DECOUPLING CAPACITORS VDD = +15V VSS = -15V V p-p = 0.63V
CAPACITANCE (pF)
8
-40 -50 -60 -70
6
4
2
-80
SOURCE OFF
-90
06119-056
-10
-5
0 VBIAS (V)
5
10
15
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 25. ADG1207 Capacitance vs. Source Voltage, 15 V Dual Supply
Figure 27. AC PSRR vs. Frequency
14 12 10
VDD = 12V VSS = 0V TA = 25C SOURCE/DRAIN ON
CAPACITANCE (pF)
DRAIN OFF 8 6 4 2 0 SOURCE OFF
0
2
4
6 VBIAS (V)
8
10
12
Figure 26. ADG1207 Capacitance vs. Source Voltage, 12 V Single Supply
06119-057
Rev. 0 | Page 15 of 20
06119-058
0 -15
-100 100
ADG1206/ADG1207 TERMINOLOGY
RON Ohmic resistance between D and S. RON Difference between the RON of any two channels. RFLAT(ON) Flatness is defined as the difference between the maximum and minimum value of on resistance as measured. IS (Off) Source leakage current when the switch is off. ID (Off) Drain leakage current when the switch is off. ID, IS (On) Channel leakage current when the switch is on. VD (VS) Analog voltage on Terminals D and S. CS (Off) Channel input capacitance for the off condition. CD (Off) Channel output capacitance for the off condition. CD, CS (On) On switch capacitance. CIN Digital input capacitance. tON (EN) Delay time between the 50% and 90% points of the digital input and the switch on condition. tOFF (EN) Delay time between the 50% and 90% points of the digital input and the switch off condition. tTRANSITION Delay time between the 50% and 90% points of the digital inputs and the switch on condition when switching from one address state to another. TBBM Off time measured between the 80% points of the switches when switching from one address state to another. VINL Maximum input voltage for Logic 0. VINH Minimum input voltage for Logic 1. IINL (IINH) Input current of the digital input. IDD Positive supply current. ISS Negative supply current. Off Isolation A measure of unwanted signal coupling through an off channel. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. Bandwidth The frequency at which the output is attenuated by 3 dB. On Response The frequency response of the on switch. THD + N The ratio of the harmonic amplitude plus noise of the signal to the fundamental. ACPSRR (AC Power Supply Rejection Ratio) Measures the ability of a part to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. The dc voltage on the device is modulated by a sine wave of 0.62 V p-p. The ratio of the amplitude of signal on the output to the amplitude of the modulation is the ACPSRR.
Rev. 0 | Page 16 of 20
ADG1206/ADG1207 TEST CIRCUITS
V S D IDS
06119-025
IS (OFF) A VS
S
D
ID (OFF) A
06119-026
ID (ON) NC S D A
06119-027
VS
VD
NC = NO CONNECT
VD
Figure 28. On Resistance
Figure 29. Off Leakage
Figure 30. On Leakage
VDD 3V ADDRESS DRIVE (VIN) 0V 50% 50%
VSS
tr < 20ns tf < 20ns
VIN
VDD A0 50 A1 A2 A3
VSS S1 S2 TO S15 S16 VS16 OUTPUT D GND 300 35pF
06119-028
VS1
tTRANSITION
tTRANSITION
90%
ADG12061
2.4V EN
OUTPUT
90%
1SIMILAR
CONNECTION FOR ADG1207.
Figure 31. Address to Output Switching Times, tTRANSITION
VDD 3V ADDRESS DRIVE (VIN) 0V VIN 50 VSS
VDD A0 A1 A2 A3
VSS S1 S2 TO S15 S16 VS
80% OUTPUT
80% 2.4V
ADG12061
EN GND D
OUTPUT
300
35pF
06119-029
tBBM
1SIMILAR
CONNECTION FOR ADG1207.
Figure 32. Break-Before-Make Delay, tBBM
VDD 3V ENABLE DRIVE (VIN) 0V 50% 50% VSS
VDD A0 A1 A2 A3
VSS S1 S2 TO S16 VS
tON (EN)
0.9VO OUTPUT
tOFF (EN)
0.9VO VIN 50
ADG12061
EN GND D
OUTPUT
300
35pF
06119-030
1SIMILAR
CONNECTION FOR ADG1207.
Figure 33. Enable Delay, tON (EN), tOFF (EN)
Rev. 0 | Page 17 of 20
ADG1206/ADG1207
VDD VSS VDD A0 A1 VIN A2 A3 RS VOUT QINJ = CL x VOUT VOUT VS VIN VSS
3V
ADG12061
S EN GND D CL 1nF VOUT
1SIMILAR
CONNECTION FOR ADG1207.
Figure 34. Charge Injection
VDD 0.1F
VSS 0.1F NETWORK ANALYZER
NETWORK ANALYZER VOUT RL 50
VDD 0.1F
VSS 0.1F
VDD S
VSS
VDD S1
VSS
50 D
50 VS VOUT
06119-031
D S2 VS
R 50
GND
RL 50
GND
VS
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
Figure 35. Off Isolation
Figure 37. Channel-to-Channel Crosstalk
VDD 0.1F
VSS 0.1F NETWORK ANALYZER
VDD 0.1F
VSS 0.1F AUDIO PRECISION
VDD S
VSS
VDD S
VSS
RS VS V p-p RL 10k VOUT
06119-035
50 VS D RL 50 VOUT
IN D VIN GND
GND
INSERTION LOSS = 20 log
VOUT WITH SWITCH VOUT WITHOUT SWITCH
06119-033
Figure 36. Bandwidth
Figure 38. THD + Noise
Rev. 0 | Page 18 of 20
06119-034
OFF ISOLATION = 20 log
06119-032
VOUT
VOUT VS
ADG1206/ADG1207 OUTLINE DIMENSIONS
9.80 9.70 9.60
28
15
4.50 4.40 4.30
1 14
6.40 BSC
PIN 1 0.65 BSC 0.15 0.05 COPLANARITY 0.10 0.30 0.19 1.20 MAX 8 0 0.75 0.60 0.45
SEATING PLANE
0.20 0.09
COMPLIANT TO JEDEC STANDARDS MO-153-AE
Figure 39. 28-Lead Thin Shrink Small Outline Package [TSSOP] (RU-28) Dimensions shown in millimeters
5.00 BSC SQ 0.45 BSC *EXPOSED PAD (TOP VIEW) 4.75 BSC SQ 2.85 2.70 SQ 2.55 0.60 0.42 0.24 0.50 BSC
24
0.60 0.42 0.24
25 32 1
PIN 1 INDICATOR
BOTTOM VIEW 0.50 0.40 0.30
17 16
8 9
12 MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM
3.50 REF
0.20 MIN
1.00 MAX 0.85 NOM
SEATING PLANE
0.30 0.23 0.18
0.20 REF
COPLANARITY 0.05
*COMPLIANT TO JEDEC STANDARDS MO-220 WITH EXCEPTION TO PADDLE ORIENTATION.
Figure 40. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm x 5 mm Body, Very Thin Quad (CP-32-2) Dimensions shown in millimeters
ORDERING GUIDE
Model ADG1206YRUZ 1 ADG1206YRUZ-REEL71 ADG1206YCPZ-REEL71 ADG1207YRUZ1 ADG1207YRUZ-REEL71 ADG1207YCPZ-REEL71
1
Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C
Description 28-Lead Thin Shrink Small Outline Package [TSSOP] 28-Lead Thin Shrink Small Outline Package [TSSOP] 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 28-Lead Thin Shrink Small Outline Package [TSSOP] 28-Lead Thin Shrink Small Outline Package [TSSOP] 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Package Option RU-28 RU-28 CP-32-2 RU-28 RU-28 CP-32-2
Z = Pb-free part.
Rev. 0 | Page 19 of 20
ADG1206/ADG1207 NOTES
(c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06119-0-7/06(0)
Rev. 0 | Page 20 of 20

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